100BASE-T1 Automotive Ethernet Protocol Analyzer with long capture sequence and API support and multiple levels of triggers.
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Product number: PGY-100BASE-T1-PA
Manufacturer: Prodigy
Description
100BASE-T1 Automotive Ethernet Protocol Analyzer is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. Automotive Ethernet interface scales up to address current and future needs of in-vehicle bus speed requirements. The need for higher-speed in-vehicle buses is increasing to support feature-rich ADAS and connected vehicle needs. Two-wire full-duplex 100BASE-T1 PAM 3 signalling is the choice of interface bus to address these needs
Prodigy Technovations 100BASE-T1 Automotive Ethernet Protocol Analyzer provides an industry-first solution for the non-intrusively passive tap of the 100BASE-T1 bus at the physical layer and ensures no latency and accurate capturing of protocol data. Powerful basic and multi-level layer 2 to layer 7 protocol trigger capabilities enables the design engineer to capture protocol activity at a specific event. PGY-100BASE-T1-PA supports continuous streaming of captured protocol data to host computer SSD/HDD enabling long-duration capture.
Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Automotive Ethernet Analyzer Test Setup
PGY-100BASE-T1-PA sniffs the automotive Ethernet bus and monitors the protocol activity between the Master and Slave ECU. Simultaneously monitoring MDIO and MDC lines and correlating with 100BASE-T1 protocol activity helps easy debug the design problems. The Automotive Ethernet Analyzer unit will extract bit values from full-duplex PAM3 signal using Prodigy’s patent-pending solution. The host computer manages the operation of the analyzer unit, and stores and analyzes the acquired data. Passive tapping of the 100BASE-T1 bus ensures the least latency in acquiring the data making this solution an industry-first Passive TAP patent-pending solution.
Powerful Trigger capabilities
PGY-100BASE-T1-PA supports the industry’s best protocol layer trigger capabilities. Users can define trigger conditions from Layer 2 to layer 7. Advanced multi-layer trigger featured with If-then-else if allows the design engineer to monitor more than one trigger condition at the same time.
Protocol Analysis
Ethernet is one of the oldest protocols widely used protocol for many applications. Design engineers are used to viewing and analyzing the protocol data in a specific format. PGY-100BASE-T1-PA Protocol Analyzer software maintains the traditional views and provides advanced analysis capabilities. Live decoding capability provides decoding with any FCS error packets.
Setup Ansicht
Analyzing Protocol data to identify the design issues is a challenging task in millions of protocol packets. PGY-100BASE-T1-PA provides statistical information about each layer packet count and error packets. This simplifies the process of isolating the errors to specific protocol packets or protocol layers. Powerful expression-based search capabilities quickly help in locating packets of interest in the acquired entire protocol data for further analysis.
Warranty
Hardware and software are covered by a one-year warranty. Probes are covered months warranty for all manufacturing defects
Technical Data
| Specification |  |
|---|---|
| Ports input | Four 100Base-T1 Ports Upgrade Two additional 100Base-T1 Port MDIO/MDC Port Two CAN Ports |
| Protocol Analysis | Layer 2 to Layer 7 Automotive Ethernet protocol Analysis MDIO/MDC Protocol Decode Upgradable to CAN Protocol Analysis |
| Protocol Views | Protocol Listing of Layer 2 Decoding of Protocol layer Packet view Tree view Line training view Analytics |
| Event Monitoring | FCS errors |
| Search and Filter | Boolean expression based search and filter capabilities |
| Capabilities Export of Results | CSV or TXT report generation |
| Host Computer System requirements | Windows® 7/8.0/8.1/10 64bit operating system. It requires RAM of 16GB but the product would give a faster response for a 32GB. The maximum storage capacity of 1GB should be available in the hard disk drive. Users can use more storage based on trace storage requirements. The Display resolution of the monitor is 1024x768 host Computer should support a USB 3.0 Interface. |
Documentation
Exerciser - Analyzer Communicationprotocol
100BASE-T1 Automotive Ethernet Protocol Analyzer
Product Nr.: PGY-100BASE-T1-PA
...show more
Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Price on request
SPMI Protocol Analyzer and Exerciser
Product Nr.: PGY-SPMI-EX-PD
...show more
Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser
- Supports SPMI v 1.0/ 2.0 specifications
- Ability to configure it as Master or Slave
- Supports Sole Master feature
- Supports Request Capable Slave (RCS) feature
- Supports the complex BUS arbitration process
- Generate different SPMI Packets
- Error injection such as parity error, ACK/NACK error, and Skip SSC error
- Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
- Simultaneously generate SPMI traffic and Protocol decode of the Bus
- Continuous streaming of protocol data to HDD/SSD
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol decoded data
- Ability to write exerciser script to combine multiple
- data frame generation at different data speeds
- USB2/3 host computer interface
- API support for automation in Python and C++
- Flexibility to upgrade to the unit for evolving SPMI Specification
- Optional Protocol Implementation Compliance Statement (PICS) supports scripts
Price on request
I2C/SPI Exerciser and Protocol Analyzer
Product Nr.: PGY-I2C/SPI-EX-PD
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Features I2C/SPI Protocol Analyzer and Exerciser
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Price on request
I3C Protocol Analyzer and Exerciser Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
I3C Protocol Analyzer and Exerciser (Light) Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD-Lite
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
JTAG Protocol Exerciser and Analyzer
Product Nr.: PGY-JTAG-EX-PD
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Features JTAG Protocol Analyzer and Exerciser
- Supports JTAG frequencies of up to 25MH
- Simultaneously generate JTAG traffic and Protocol decode of the Bus
- JTAG Master Capability
- Variable JTAG Data speeds and Duty cycle
- User-defined TCK & TDI Delays
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
PCIe Gen3/4 Protocol Analyzer
Product Nr.: PGY-PCIeGen3/4-PA
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Features PCIe Protocol Analyzer
- PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
- Currently supports four lane PCIeGen1/2/3/4 Bus.
- Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
- Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Trigger based on TS1, TS2, TLP and DLLP Packet content.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition¹.
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable enables the unit to easy maintain for latest feature set.
Price on request
PMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-PM-Bus-EX-PD
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Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Price on request
QSPI Exerciser and Protocol Analyzer
Product Nr.: PGY-QSPI-EX-PD
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Features QSPI Protocol Exerciser and Analyzer
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
RFFE Protocol Exerciser and Analyzer
Product Nr.: PGY-RFFE-EX-PD
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Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Price on request
SMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-SM-Bus-EX-PD
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Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer
- Supports SMBus 3.4Mbps Speed
- Ability to configure it as Master or Slave
- Simultaneously generate SMBus traffic and Protocol decode of the Bus
- SMBus Master and Slaves
- Error Injection ACK/NACK errors
- Variable SMBus data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
SMI (MDIO) Protocol Exerciser & Analysator
Product Nr.: PGY-SMI-EX-PD
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Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser
- Supports SMI (MDIO) speeds up to 25MHz
- Configuration as master or slave
- Simultaneous SMI traffic generation and protocol decoding
- Support for SMI clause 22 and 45
- Variable SMI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- Timing diagram of the protocol-decoded bus
- Listing view of log activity
- Ability to write a training script to combine the generation of multiple data frames at different data rates
- USB 2.0/3.0 interface for host computer
- API support for automation in Python or C++
Price on request
UART Protocol Exerciser and Analyzer
Product Nr.: PGY-UART-EX-PD
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Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request