Exerciser & Analyzer for communication protocols

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Product Nr.: PGY-100BASE-T1-PA
100BASE-T1 Automotive Ethernet Protocol Analyzer with long capture sequence and API support and multiple levels of triggers.
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Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Price on request

Product Nr.: PGY-SPMI-EX-PD
SPMI Protocol Analyzer and Exerciser allow decoding and analyzing the SPMI protocol and debugging the SPMI protocol.
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Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser
- Supports SPMI v 1.0/ 2.0 specifications
- Ability to configure it as Master or Slave
- Supports Sole Master feature
- Supports Request Capable Slave (RCS) feature
- Supports the complex BUS arbitration process
- Generate different SPMI Packets
- Error injection such as parity error, ACK/NACK error, and Skip SSC error
- Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
- Simultaneously generate SPMI traffic and Protocol decode of the Bus
- Continuous streaming of protocol data to HDD/SSD
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol decoded data
- Ability to write exerciser script to combine multiple
- data frame generation at different data speeds
- USB2/3 host computer interface
- API support for automation in Python and C++
- Flexibility to upgrade to the unit for evolving SPMI Specification
- Optional Protocol Implementation Compliance Statement (PICS) supports scripts
Price on request

Product Nr.: PGY-I2C/SPI-EX-PD
I2C Protocol Analyzer and SPI Protocol Analyzer with long capture sequence and API support and multiple level of triggers.
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Features I2C/SPI Protocol Analyzer and Exerciser
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Price on request

Product Nr.: PGY-I3C-EX-PD
The I3C Protocol Analyzer and Exerciser allow decoding and analyzing the I3C protocol and debugging of the I3C protocol.
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request

Product Nr.: PGY-I3C-EX-PD-Lite
The I3C Protocol Analyzer and Exerciser allow decoding and analyzing the I3C protocol and debugging of the I3C protocol.
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request

Product Nr.: PGY-JTAG-EX-PD
Test your JTAG designs and configure master/slave, generate JTAG traffic and decode the JTAG protocol.
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Features JTAG Protocol Analyzer and Exerciser
- Supports JTAG frequencies of up to 25MH
- Simultaneously generate JTAG traffic and Protocol decode of the Bus
- JTAG Master Capability
- Variable JTAG Data speeds and Duty cycle
- User-defined TCK & TDI Delays
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request

Product Nr.: PGY-PCIeGen3/4-PA
PCIe Protocol Analyzer provides protocol analysis up to PCIe Gen4. You can easily capture and record traces at 2.5, 5.0, 8 and 16GT/s on specific events.
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Features PCIe Protocol Analyzer
- PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
- Currently supports four lane PCIeGen1/2/3/4 Bus.
- Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
- Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Trigger based on TS1, TS2, TLP and DLLP Packet content.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition¹.
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable enables the unit to easy maintain for latest feature set.
Price on request

Product Nr.: PGY-PM-Bus-EX-PD
PMBus Protocol Analyzer has multiple features to capture and debug communication in the DUT.
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Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Price on request

Product Nr.: PGY-QSPI-EX-PD
Test your QSPI designs effectively! Configure master/slave, generate QSPI traffic and decode the QSPI protocol.
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Features QSPI Protocol Exerciser and Analyzer
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request

Product Nr.: PGY-RFFE-EX-PD
Test your RFFE designs effectively! Configure master/slave, generate RFFE traffic and decode the RFFE protocol.
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Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Price on request

Product Nr.: PGY-SM-Bus-EX-PD
SMBus Protocol Analyzer (PGY-SMBus-EX-PD) has multiple features to capture and debug communication in the DUT.
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Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer
- Supports SMBus 3.4Mbps Speed
- Ability to configure it as Master or Slave
- Simultaneously generate SMBus traffic and Protocol decode of the Bus
- SMBus Master and Slaves
- Error Injection ACK/NACK errors
- Variable SMBus data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request

Product Nr.: PGY-SMI-EX-PD
SMI (MDIO) Protocol Analyzer and Exerciser allow decoding and analyzing the SMI protocol and debugging the SMI protocol.
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Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser
- Supports SMI (MDIO) speeds up to 25MHz
- Configuration as master or slave
- Simultaneous SMI traffic generation and protocol decoding
- Support for SMI clause 22 and 45
- Variable SMI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- Timing diagram of the protocol-decoded bus
- Listing view of log activity
- Ability to write a training script to combine the generation of multiple data frames at different data rates
- USB 2.0/3.0 interface for host computer
- API support for automation in Python or C++
Price on request

Product Nr.: PGY-UART-EX-PD
UART Protocol Analyzer has multiple features to capture and debug communication in the DUT.
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Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request