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Description
I3C Protocol Analyzer (PGY-I3C-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. I3C Serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive industries. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data-intensive applications.
The I3C serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive industries. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data-intensive applications. The PGY-I3C-EX-PD is the leading instrument that enables the design and test engineers to test the I3C designs for their specifications by configuring the PGY-I3C-EX-PD as Master/Slave to generate I3C traffic with error injection capabilities and to decode I3C protocol packets.
Features I3C Protocol Analyzer und Exerciser
- Supports v1.0/v1.1 Specifications
- Ability to configure it as Master or Slave.
- Ability to configure BCR, LVR, and DCR registers.
- Simultaneously generate I3C traffic and Protocol decode of the Bus.
- Optional Compliance Test Specifications (CTS) test script support.
- Supports legacy I2C slaves and Master.
- Generate different I3C SDR and HDR Packets.
- Supports IBI and Hot Plug capabilities.
- Error Injection such as CRC errors, parity errors, and ACK/NACK errors.
- Variable I3C data speeds and duty cycle.
- PMIC device support as per JEDEC DDR5 spec requirement.
- Margin test capability: Voltage and timing variation.
- Continuous streaming of protocol data between the instrument and host computer.
- Timing diagram of Protocol decoded bus.
- Listing view of Protocol activity.
- Error Analysis in Protocol Decode.
- Ability to write exerciser script to combine multiple data frame generation at different data speeds.
- USB2/3 host computer interface.
- API support for automation in Python or C++.
*v1.1 supports only one lane commands
Multi-domain View
Multi-domain View provides the complete view of I3C Protocol activity in a single GUI. Users can easily set up the analyzer to generate I3C/I2C traffic using the GUI or script. Users can set different trigger conditions from the setup menu to capture protocol activity at specific events and decode the transition between the Master and Slave. The decoded results can be viewed in the timing diagram and protocol listing windows with auto-correlation. State machine view provides switching of state machine between master and slave for design validation. This comprehensive view of information makes it an industry-best offering and an easy-to-use solution to debug the I3C protocol activity.
Exerciser
PGY-I3C-EX-PD supports I3C traffic generation using GUI and Script. Users can perform simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in the real world including error injections. In the below sample script users can generate I3C traffic as below:
- Script line #10: Set system Frequency 500KHz, Duty cycle to 50%, CLK to data delay to 10ns (default), start to restart setup time to 20ns (default)
- Script line #12: SETMWL
- Script line #13: Set system inter message gap to 16us
- Script line #14: SETMRL
Timing Diagram and Protocol Listing View
The timing view provides the plot of SCL and SDA signals with bus diagram information. Overlayingofprotocol bits on the digital timing waveform helps in the easy debugging of protocol decoded data. Cursor and zoom features make it convenient to analyze protocol in timing diagrams for any timing error. The protocol window provides the decoded packet information in each state and all packet details with error info in the packet. The selected frame in the protocol listing window will be auto-correlated in the timing view to view the timing information of the packet.
Powerful Trigger Capabilities
PGY-I3C-EX-PD supports auto, simple, and advanced trigger capabilities. The analyzer can trigger any of the protocol packets such as broadcast, directed, or private messages. Advanced trigger provides the flexibility to monitor multiple trigger conditions and can set multiple state trigger machines.
Minimum computer requirements
Microsoft Windows® 8, Windows 7, 16GB RAM; memory with at least 50GB of hard drive space to store captured data. Display with a resolution of at least 1024x768.
Warranty
Hardware and software are covered by a one-year warranty. Probes are covered by a three-month warranty for all manufacturing defects
Technical Data
| Specification |  |
|---|---|
| Configurable | 1 Master + 3 Slaves or 1 Secondary Master + 2 Slaves |
| I3C / I2C Traffic Generation | Custom I3C / I2C traffic generation (Simulate real world network traffic) |
| SCL Frequency | 1Hz to 12.5MHz Note: Prodigy device supports up to 10MHz at 1V frequency as a slave |
| Configurable Voltage Level Drive | 0.9V to 3.4V Steps: 0.9 – 1.27 V (In steps of 5mV) 1.27 – 1.95V (In steps of 10mV) 1.95 - 3.4V (In steps of 30mV) |
| Hot Join | Yes |
| IBI | Yes |
| CCC Support | All CCC are supported in Master slide. All CCC are supported in Slave except SETXTIME, ENTTM, ENTAS |
| SCL Duty Cycle variation | User Defined (In Fine resolutions of 10ns) |
| SCL & SDA Delay | User Defined (In Fine resolutions of 18ps) |
| Delay between two messages | User Defined (In Fine resolutions of ns, us, ms and seconds) |
| Error injection | S0 to S5 types of errors specified in I3C specifications. CRC errors in DDR traffic. Preamble errors in DDR traffic ACK / NACK Errors (Slave) Master Abort. Non-Standard Frames. Non-Standard Start, Stop and HDR exit patterns, slave reset Save and Load Scripts. |
| API Support | Support for Automation of operation using Python or C++ |
| Supports | I3C & I2C protocol decode |
| Protocol Views | Timing Diagram View Protocol Listing View Bus-Diagram to display Protocol packets with timing diagram plot |
| Protocol Trigger | Auto (Trigger on any packet) Simple (Trigger on user defined I3C or I2C packet) Advanced (Multi-state & multi-level trigger with timer capability) |
| Capture Duration | Continuous streaming Protocol Data to host HDD/SSD |
| Protocol Error Report | S0 to S5 types of errors specified in the I3C specifications CRC errors in DDR traffic Preamble errors in DDR traffic ACK /NACK Errors (Slave) Master Abort Non-Standard frames Non-standard Start, Stop and HDR exit patterns. |
| Host Connectivity | USB 3.0 / 2.0 interface |
| Model | | | Notes |
|---|---|---|---|
| Configurable | 1 master + 1 slave | 1 master + 3 slaves 1 Secondary Master +2 Slaves | |
| I3C / I2C traffic generation | ✓ | ✓ | Custom I3C/I2C traffic generation |
| SCL Frequency | ✓ | ✓ | 400KHz to 13.5MHz |
| Simulate real network traffic | X | ✓ | |
| Configurable operating voltage | 1.2V/1.8V/2.5V/3.3V | Step (100mV) 1V to 3.3V | |
| Hot Join | ✓ | ✓ | |
| CCC support | ✓ | ✓ | All CCC are supported in master mode All CCC are supported as slave (Excluding SETXTIME, ENTTMENTAS) |
| SCL Duty Cycle Variation | X | ✓ | Custom |
| SCL & SDA Delay | X | ✓ | Custom |
| Communication Delay | X | ✓ | Custom |
| Error Injection | X | ✓ | S0 to S5 error types according to I3C Specifications CRC error in DDR traffic Preamble error in DDR traffic ACK / NACK error (slave) Master Abortion Non-standard frames Non-standard start, stop and HDR exit patterns, slave reset |
| API support | X | ✓ | |
| Log Analysis | |||
| model | LITE version | Full version | Notes |
| I3C / I2C protocol decoding | ✓ | ✓ | |
| Log Views | ✓ | ✓ | Timing Diagram View Protocol List View Bus diagram to display protocol packets with Timing Diagram Plot |
| Protocol Trigger | ✓ (No advanced trigger options) | ✓ | Auto (trigger on each packet) Simple (trigger on custom I3C or I2C Package) Advanced (Multistate & Multilevel Trigger with Timer capability) |
| recording length | ✓ | ✓ | Continuous streaming of log data to HDD/SSD |
| Interfaces to the host | ✓ | ✓ | USB 3.0 / 2.0 |
| Log error report | ✓ | ✓ | Error types S0 to S5 specified in the I3C specifications CRC error in DDR traffic Preamble error in DDR traffic ACK/NACK error (slave) Master Abort Not Standard frames Non-standard start, stop and HDR seed pattern. |
Documentation
Exerciser - Analyzer Communicationprotocol
Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Price on request
Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser
- Supports SPMI v 1.0/ 2.0 specifications
- Ability to configure it as Master or Slave
- Supports Sole Master feature
- Supports Request Capable Slave (RCS) feature
- Supports the complex BUS arbitration process
- Generate different SPMI Packets
- Error injection such as parity error, ACK/NACK error, and Skip SSC error
- Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
- Simultaneously generate SPMI traffic and Protocol decode of the Bus
- Continuous streaming of protocol data to HDD/SSD
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol decoded data
- Ability to write exerciser script to combine multiple
- data frame generation at different data speeds
- USB2/3 host computer interface
- API support for automation in Python and C++
- Flexibility to upgrade to the unit for evolving SPMI Specification
- Optional Protocol Implementation Compliance Statement (PICS) supports scripts
Price on request
Features I2C/SPI Protocol Analyzer and Exerciser
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Price on request
Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
Features JTAG Protocol Analyzer and Exerciser
- Supports JTAG frequencies of up to 25MH
- Simultaneously generate JTAG traffic and Protocol decode of the Bus
- JTAG Master Capability
- Variable JTAG Data speeds and Duty cycle
- User-defined TCK & TDI Delays
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
Features PCIe Protocol Analyzer
- PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
- Currently supports four lane PCIeGen1/2/3/4 Bus.
- Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
- Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Trigger based on TS1, TS2, TLP and DLLP Packet content.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition¹.
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable enables the unit to easy maintain for latest feature set.
Price on request
Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Price on request
Features QSPI Protocol Exerciser and Analyzer
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Price on request
Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer
- Supports SMBus 3.4Mbps Speed
- Ability to configure it as Master or Slave
- Simultaneously generate SMBus traffic and Protocol decode of the Bus
- SMBus Master and Slaves
- Error Injection ACK/NACK errors
- Variable SMBus data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser
- Supports SMI (MDIO) speeds up to 25MHz
- Configuration as master or slave
- Simultaneous SMI traffic generation and protocol decoding
- Support for SMI clause 22 and 45
- Variable SMI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- Timing diagram of the protocol-decoded bus
- Listing view of log activity
- Ability to write a training script to combine the generation of multiple data frames at different data rates
- USB 2.0/3.0 interface for host computer
- API support for automation in Python or C++
Price on request
Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request