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Description
The PGY-PCIeLP-SBA PCIe Low Power Side Band Signal Analyser measures the timing of side band signals and reports errors during the low power input and input time over a long period of time, allowing test engineers to test and debug the M.2 SSD devices under different operating conditions.
PGY-PCIeLP-SBA monitors the CLKREQ, REFCLK, PERSET and PWR signals of the M.2 interface under different operating conditions. It measures the timing of these signals according to the PCIe and M.2 interface specifications. The user can also set a hardware-based trigger for specific timing measurements and is notified during the automated long-term tests. The user interface displays a timing diagram with an abstract view of the 100MHz Ref Clk state, low power state, restart, power recycle and power-on state as the test cases are executed.
Features PCIe Low Power Side Band Signal Analyser
- Cost-effective logic analyser with continuous streaming function for monitoring sideband signals
- Records the timing waveforms of PWR, CLKREQ, PERSET and REFCLK
- Power-ON state
- Restart
- Power-saving entry and exit from and to the L0 state
- Measures timing parameters
- Signals the failure of timing parameters
- Trigger for timing parameter failure
- Support for low latency reports to overwrite T-CRON parameters
- Report generation
PGY-PCIeLP-SBA has an M.2 extender card with access to all sideband signals that can be connected to the PCIe Low Power Sideband Signal Analyser. The software runs on a Windows PC and allows the analyser to be configured for measurements and trigger conditions. It continuously records the timing waveforms and updates the timing measurement overview with statistical and detailed information.
Configuration panel
The configuration allows users to easily select the timing parameters to be measured and set the trigger when these parameters fail. The user can set the duration of the recording (it can be several hours) or stop the analysis manually. The selection of pre- and post-trigger offers the possibility to view the data around the trigger condition.
PGY-PCIeLP-SBA provides powerful debugging functions that allow the user to detect errors in the recorded data:
- Linking the specific measurement to the timing waveform using markers
- Sorting the specific measurement to display all hits
- Sorting of failed or successful measurements
- Support of the latency tolerance report
Warranty
Hardware and software are covered by a one-year warranty. The probes are covered by a monthly warranty on all manufacturing defects
Technical Data
| Specification |  |
|---|---|
Measurement parameters | Parameter Description |
TCRH OFF | CLQREQ# de-asserted high to clock parked |
TCRL ON | CLQREQ# is set to low to activate the clock |
TPVGL | Power Valid to PERST# input active |
TPERST#CLK | REFCLK stable before PERST# deassertion |
TPERST | Enforcement time of PERST# |
Documentation
Exerciser & Analyser from Prodigy
