Mobile Bus Host Adapter

Features I3C Protocol Analyzer und Exerciser

*v1.1 supports only one lane commands

Features I3C Protocol Analyzer und Exerciser

*v1.1 supports only one lane commands

Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser

• Supports SPMI v 1.0/ 2.0 specifications
• Ability to configure it as Master or Slave
• Supports Sole Master feature
• Supports Request Capable Slave (RCS) feature
• Supports the complex BUS arbitration process
• Generate different SPMI Packets
• Error injection such as parity error, ACK/NACK error, and Skip SSC error
• Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
• Simultaneously generate SPMI traffic and Protocol decode of the Bus
• Continuous streaming of protocol data to HDD/SSD
• The timing diagram of the Protocol decoded bus
• Listing view of Protocol activity
• Error Analysis in Protocol decoded data
• Ability to write exerciser script to combine multiple
• data frame generation at different data speeds
• USB2/3 host computer interface
• API support for automation in Python and C++
• Flexibility to upgrade to the unit for evolving SPMI Specification
• Optional Protocol Implementation Compliance Statement (PICS) supports scripts

Features RFFE Protocol Analyzer and Exerciser

• Supports RFFE2.0/2.1 Specification
• Ability to configure it as Master or Slave
• Generate different RFFE at full speed and half of full frequency speed
• Error Injection such as parity errors and ACK/NACK errors
• Variable RFFE data speeds
• Simultaneously generate RFFE traffic and Protocol decode of the Bus
• The timing diagram of the Protocol decoded bus
• Listing view of Protocol activity
• Error Analysis in Protocol Decode
• Ability to write exerciser script to combine multiple data frame generation at different data speeds
• USB2/3 host computer interface
• Flexibility to upgrade to the unit for evolving RFFE Specification

Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer

• Supports custom UART traffic generation
• Simultaneously generate UART traffic and Protocol decode of the bus
• Variable UART baud rates
• Continuous streaming of protocol data to the host computer to provide a large buffer
• A timing diagram of Protocol decoded bus
• Listing view of Protocol activity
• Error Analysis in Protocol Decode
• Ability to write exerciser script to combine multiple data frame generation at different data speeds
• USB 2.0/3.0 host computer interface
• API support for automation in Python or C++

Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer

• Supports PMBus Specifications. 
• Ability to configure it as Master/Slave. 
• Variable data speeds. 
• Generate PMbus traffic and protocol decode of the bus. 
• A timing diagram of the protocol decoded bus. 
• Listing view of protocol activity. 
• Ability to write exerciser script to combine multiple frame generation at different data speeds. 
• USB 2/3 host computer interface. 
• Continuous streaming of protocol data to host computer to provide a large buffer.
• API support for automation in python or C++.

Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer

• Supports SMBus 3.4Mbps Speed
• Ability to configure it as Master or Slave
• Simultaneously generate SMBus traffic and Protocol decode of the Bus
• SMBus Master and Slaves
• Error Injection ACK/NACK errors
• Variable SMBus data speeds and duty cycle
• Continuous streaming of protocol data to the host computer to provide a large buffer
• A timing diagram of Protocol decoded bus
• Listing view of Protocol activity
• Error Analysis in Protocol Decode
• Ability to write exerciser script to combine multiple data frame generation at different data speeds
• USB 2.0/3.0 host computer interface
• API support for automation in Python or C++

Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser

• Supports SMI (MDIO) speeds up to 25MHz
• Configuration as master or slave
• Simultaneous SMI traffic generation and protocol decoding
• Support for SMI clause 22 and 45
• Variable SMI data speeds and duty cycle
• Continuous streaming of protocol data to the host computer to provide a large buffer
• Timing diagram of the protocol-decoded bus
• Listing view of log activity
• Ability to write a training script to combine the generation of multiple data frames at different data rates
• USB 2.0/3.0 interface for host computer
• API support for automation in Python or C++

Features

• I3C controller in SDR and HDR-DDR mode, I3C target in SDR and HDR-DDR mode and I3C target with secondary controller function. I3C Basic v1.1.1 (downwards compatible with I3C Baisc v1.0).
• Wide voltage range from 0.8 V to 3.3 V
• Push-pull modes: 3.75 MHz to 12.5 MHz
• Open drain modes: 100 kHz to 4.17 MHz
• Dynamic address assignments for flexible device communication.
• Comprehensive transaction types, including private i3c write and read transactions and CCC (Common Command Code) transactions.
• Legacy I2C backward compatibility for seamless integration.
• Advanced features such as in-band interrupts (IBIs), hot-join and controller role handover.
• Efficient data operations with extensive read and write functions.
• Dynamic target device table that can be configured and automatically updated by the user.

• Comprehensive support for the I2C controller function.
• Versatile voltage setting from 1.2 V to 3.3 V
• Adjustable SCL clock frequency to adapt to different communication requirements in the range of 10 kHz to 1 MHz.
• Optimised operations to facilitate both writing to and reading from devices.
• Provides the ability to set specific register addresses.
• Supports "non-stop" or "repeated start" conditions.
• Simplified parameter configuration for optimised communication.