Test your RFFE designs effectively! Configure master/slave, generate RFFE traffic and decode the RFFE protocol.
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Product number: PGY-RFFE-EX-PD
Manufacturer: Prodigy
Description
RFFE Protocol Analyzer(PGY-RFFE-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. The RF Front-end control interface (RFFE) Serial bus interface is emerging as a choice for controlling RF front-end devices. There is a variety of front-end devices such as Power Amplifiers (PA), Low-Nose Amplifiers (LNA), filters, switches, power management modules, and antenna tuners. It is widely used on mobile devices.
Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Multidomain-View
Multi-domain View provides the complete view of RFFE Protocol activity in a single GUI. Users can easily set up the analyzer to generate RFFE traffic using a GUI or script. Users can set different trigger conditions from the setup menu to capture Protocol activity at specific events and decode the protocol transactions between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the RFFE protocol activity.
Exerciser
PGY-RFFE-EX-PD supports RFFE traffic generation using GUI and Script. Users can generate simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in the real-world including error injections. In this sample script user can generate RFFE traffic as below:
- Script line #4: REG Write to the slave with USID 5
- Script line #5: REG Read to the slave with USID 5
- Script line #8: EXT REG Write to the slave with USID 5
- Script line #9: EXT REG Read to the slave with USID 5
Timing Diagram and Protocol Listing View
The timing view provides the plot of SCLK and SDATA signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors. The protocol window provides the decoded packet information in each state and all packet details. The selected frame in the Protocol listing window will be auto-correlated in the timing view to view the timing information of the packet.
Powerful Trigger Capabilities
PGY-RFFE-EX-PD supports auto, simple, and advanced trigger capabilities. The analyzer can trigger on any of the Protocol packets such as Ext. Reg. Write, Ext. Reg, read and so forth message. Advanced Trigger provides the flexibility to monitor multiple trigger conditions and can set multiple state trigger machines.
Warranty
Hardware and software are covered by a one-year warranty. Probes are covered months warranty for all manufacturing defects
Technical Data
| Spezifiation |  |
|---|---|
| Configurable | 1 Master + 4 Slaves |
| RFFE Traffic Generation | Custom RFFE Traffic Generation |
| SCL Frequency | 32KHz to 52 MHz |
| Voltage Drive Level | 1.2V and 1.8V |
| SCL Duty Cycle variation | 25%, 50% and 75% |
| SCL and SDA delay | User defined in multiples of 5.2ns |
| Delay between two messages | User-Defined |
| Error injection | Parity error injection |
| Supports | RFFE 2.0/2.1 protocol decode |
| Protocol Views | Timing Diagram View Protocol Listing View Bus-Diagram to display Protocol packets with timing diagram plot |
| Protocol Trigger | Auto (Trigger on any packet) Simple (Trigger on any user defined RFFE packet) Advanced (Multi-state & multi-level trigger capability) |
| Capture Duration | Continuous streaming Protocol Data |
| Protocol Error Report | Parity |
| Host Connectivity | USB 3.0 / 2.0 interface |
Documentation
Exerciser - Analyzer
100BASE-T1 Automotive Ethernet Protocol Analyzer
Product Nr.: PGY-100BASE-T1-PA
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Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Price on request
SPMI Protocol Analyzer and Exerciser
Product Nr.: PGY-SPMI-EX-PD
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Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser
- Supports SPMI v 1.0/ 2.0 specifications
- Ability to configure it as Master or Slave
- Supports Sole Master feature
- Supports Request Capable Slave (RCS) feature
- Supports the complex BUS arbitration process
- Generate different SPMI Packets
- Error injection such as parity error, ACK/NACK error, and Skip SSC error
- Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
- Simultaneously generate SPMI traffic and Protocol decode of the Bus
- Continuous streaming of protocol data to HDD/SSD
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol decoded data
- Ability to write exerciser script to combine multiple
- data frame generation at different data speeds
- USB2/3 host computer interface
- API support for automation in Python and C++
- Flexibility to upgrade to the unit for evolving SPMI Specification
- Optional Protocol Implementation Compliance Statement (PICS) supports scripts
Price on request
I2C/SPI Exerciser and Protocol Analyzer
Product Nr.: PGY-I2C/SPI-EX-PD
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Features I2C/SPI Protocol Analyzer and Exerciser
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Price on request
I3C Protocol Analyzer and Exerciser Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
I3C Protocol Analyzer and Exerciser (Light) Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD-Lite
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
JTAG Protocol Exerciser and Analyzer
Product Nr.: PGY-JTAG-EX-PD
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Features JTAG Protocol Analyzer and Exerciser
- Supports JTAG frequencies of up to 25MH
- Simultaneously generate JTAG traffic and Protocol decode of the Bus
- JTAG Master Capability
- Variable JTAG Data speeds and Duty cycle
- User-defined TCK & TDI Delays
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
PCIe Gen3/4 Protocol Analyzer
Product Nr.: PGY-PCIeGen3/4-PA
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Features PCIe Protocol Analyzer
- PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
- Currently supports four lane PCIeGen1/2/3/4 Bus.
- Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
- Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Trigger based on TS1, TS2, TLP and DLLP Packet content.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition¹.
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable enables the unit to easy maintain for latest feature set.
Price on request
PMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-PM-Bus-EX-PD
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Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Price on request
QSPI Exerciser and Protocol Analyzer
Product Nr.: PGY-QSPI-EX-PD
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Features QSPI Protocol Exerciser and Analyzer
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
RFFE Protocol Exerciser and Analyzer
Product Nr.: PGY-RFFE-EX-PD
...show more
Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Price on request
SMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-SM-Bus-EX-PD
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Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer
- Supports SMBus 3.4Mbps Speed
- Ability to configure it as Master or Slave
- Simultaneously generate SMBus traffic and Protocol decode of the Bus
- SMBus Master and Slaves
- Error Injection ACK/NACK errors
- Variable SMBus data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
SMI (MDIO) Protocol Exerciser & Analysator
Product Nr.: PGY-SMI-EX-PD
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Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser
- Supports SMI (MDIO) speeds up to 25MHz
- Configuration as master or slave
- Simultaneous SMI traffic generation and protocol decoding
- Support for SMI clause 22 and 45
- Variable SMI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- Timing diagram of the protocol-decoded bus
- Listing view of log activity
- Ability to write a training script to combine the generation of multiple data frames at different data rates
- USB 2.0/3.0 interface for host computer
- API support for automation in Python or C++
Price on request
UART Protocol Exerciser and Analyzer
Product Nr.: PGY-UART-EX-PD
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Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request