Prodigy RFFE Protocol Exerciser and Analyzer

Test your RFFE designs effectively! Configure master/slave, generate RFFE traffic and decode the RFFE protocol.

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Product number: PGY-RFFE-EX-PD
Manufacturer: Prodigy

Description

RFFE Protocol Analyzer(PGY-RFFE-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. The RF Front-end control interface (RFFE) Serial bus interface is emerging as a choice for controlling RF front-end devices. There is a variety of front-end devices such as Power Amplifiers (PA), Low-Nose Amplifiers (LNA), filters, switches, power management modules, and antenna tuners. It is widely used on mobile devices.

Features RFFE Protocol Analyzer and Exerciser

  • Supports RFFE2.0/2.1 Specification
  • Ability to configure it as Master or Slave
  • Generate different RFFE at full speed and half of full frequency speed
  • Error Injection such as parity errors and ACK/NACK errors
  • Variable RFFE data speeds
  • Simultaneously generate RFFE traffic and Protocol decode of the Bus
  • The timing diagram of the Protocol decoded bus
  • Listing view of Protocol activity
  • Error Analysis in Protocol Decode
  • Ability to write exerciser script to combine multiple data frame generation at different data speeds
  • USB2/3 host computer interface
  • Flexibility to upgrade to the unit for evolving RFFE Specification

Multidomain-View

PGY-SSM SD SDIO eMMC Protocol Analyzer Computer Setup

Multi-domain View provides the complete view of RFFE Protocol activity in a single GUI. Users can easily set up the analyzer to generate RFFE traffic using a GUI or script. Users can set different trigger conditions from the setup menu to capture Protocol activity at specific events and decode the protocol transactions between Master and Slave. The decoded results can be viewed in the timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it the industry’s best, offering an easy-to-use solution to debug the RFFE protocol activity.

Exerciser

PGY-RFFE-EX-PD supports RFFE traffic generation using GUI and Script. Users can generate simple traffic generation using the GUI to test the DUT. Script-based GUI provides flexibility to emulate the complete expected traffic in the real-world including error injections. In this sample script user can generate RFFE traffic as below:

  • Script line #4: REG Write to the slave with USID 5
  • Script line #5: REG Read to the slave with USID 5
  • Script line #8: EXT REG Write to the slave with USID 5
  • Script line #9: EXT REG Read to the slave with USID 5
PGY-I3C-EX-PD Protocol Analyzer Bus Configuration
 

Timing Diagram and Protocol Listing View

PGY-I3C-EX-PD I3C Protocol-Analyzer-Timing-view
PGY-I3C-EX-PD I3C Protocol-Analyzer Timing-decoded-result

The timing view provides the plot of SCLK and SDATA signals with a bus diagram. Overlaying of Protocol bits on the digital timing waveform will help easy debugging of Protocol decoded data. Cursor and Zoom features will make it convenient to analyze Protocol in the timing diagram for any timing errors. The protocol window provides the decoded packet information in each state and all packet details. The selected frame in the Protocol listing window will be auto-correlated in the timing view to view the timing information of the packet.

 Powerful Trigger Capabilities

PGY-RFFE-EX-PD supports auto, simple, and advanced trigger capabilities. The analyzer can trigger on any of the Protocol packets such as Ext. Reg. Write, Ext. Reg, read and so forth message. Advanced Trigger provides the flexibility to monitor multiple trigger conditions and can set multiple state trigger machines.

PGY-I3C-EX-PD I3C Protocol-Analyzer Powerful trigger capabilities

Warranty

Hardware and software are covered by a one-year warranty. Probes are covered months warranty for all manufacturing defects

Productvideo

QSPI Protocol Analysis and Debug
Introduction to QSPI

Technical Data

SpezifiationPGY-RFFE-EX-PD RFFE Protocol-Analyzer Product
Configurable1 Master + 4 Slaves
RFFE Traffic Generation
Custom RFFE Traffic Generation
SCL Frequency32KHz to 52 MHz
Voltage Drive Level1.2V and 1.8V
SCL Duty Cycle variation25%, 50% and 75%
SCL and SDA delayUser defined in multiples of 5.2ns
Delay between two messages User-Defined
Error injectionParity error injection
SupportsRFFE 2.0/2.1 protocol decode
Protocol ViewsTiming Diagram View
Protocol Listing View
Bus-Diagram to display Protocol packets with timing diagram plot
Protocol TriggerAuto (Trigger on any packet)
Simple (Trigger on any user defined RFFE packet)
Advanced (Multi-state & multi-level trigger capability)
Capture DurationContinuous streaming Protocol Data
Protocol Error ReportParity
Host ConnectivityUSB 3.0 / 2.0 interface

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