.jpg){kind=icon}
.jpg){kind=icon}
.jpg)
.jpg)
.jpg)
.jpg)
Description
The PGY-SRIO-PA is a powerful and easy-to-use Serial RapidIO Protocol Analyzer that enables developers and validation engineers to efficiently analyse SRIO protocol traffic. PGY-SRIO-PA supports RapidIO Gen1 and Gen2 signalling with data rates of up to 10 Gbaud per lane. It instantly decodes all RapidIO 4.1 packet formats and performs error analysis so engineers can accurately analyse host-device interactions.
PGY-SRIO-PA is the industry's best Serial Rapid IO Protocol Analyser. It captures SRIO traffic using hardware-based simple and advanced if-then-else triggers, hardware filters and detailed protocol analyses, enabling efficient testing and debugging of SRIO interfaces and saving development time.
Whether in the lab or in the field, the PGY-SRIO Protocol Analyser provides engineers with a compact, field-ready and robust solution for protocol conformance testing, debugging and system validation for a wide range of SRIO-enabled applications.
Features Serial RapidIO Protocol Analyser
- Supports Serial RapidIO Gen1 and Gen2 protocols with real-time protocol decoding.
- Works with 1.25/ 2.5/3.125/5.0/6.25/10 per lane (user selectable).
- Supports 1-lane and 4-lane link widths with flexible configuration via the GUI
- Two QSFP+ ports for simultaneous capture of Link A and Link B traffic
- Support of SFP+ adapters for single-lane tests with optical or copper modules
- Up to 64 GB deep acquisition buffer with configurable pre-trigger depth
- Real-time decoding of maintenance, messaging, doorbell, NWRITE and NREAD packets
- Complete decoding of control symbols including SOP, EOP, REPLAY, LINK requests
- Hardware-based triggering on packet fields, control symbols or external inputs
- Advanced trigger logic including state-based IFTHEN-ELSE sequences
- Hardware filtering to ignore irrelevant packets during capture
- Powerful search and post-capture filtering tools in the GUI for detailed analyses
- Link-level symbol views for analysing low-level activities and IDLE patterns
- Time-correlated dual-trace view for side-by-side comparisons of A→B and B→A
- Export of decoded results in CSV or TXT format for offline verification
- Trigger-in and trigger-out ports for integration into test systems (LVTTL-compatible)
- Easy-to-use Windows and Linux GUI for setup, acquisition and analysis
- High-speed interface USB 3.0 for fast data transfer and minimised set-up time
- Compact, bench-friendly hardware ideal for troubleshooting in the lab and field
- Field upgradeable for easy maintenance and remote firmware upgrade to the latest feature set
Warranty
Hardware and software are covered by a one-year warranty. The probes are covered by a monthly warranty on all manufacturing defects
Technical Data
Specification |
|
Protocol support | RapidIO specification v4.1 - Class 1, Class 2 |
Supported baud rates | 1.25 / 2.5 / 3.125 / 5.0 / 6.25 / 10.0 Gbaud (user selectable) |
Link width | 1-lane (via SFP+ adapter), 4-lane (via QSFP+ connector) |
Connectors | 2× QSFP+ connectors (1 for Link A, 1 for Link B); Trigger In/Out - SMB (LVTTL) |
Acquisition memory (buffer) | Up to 64 GB ring buffer; 1 GB standard with adjustable pre-trigger (125 |
Trigger options | Manual, protocol-based, external (input), extended If-Then-Else machine |
Filter capabilities | Hardware filter for packets and control symbols; software-based |
Raw data mode | Symbol level (after 8b/10b decoding), full field decoding available |
Host interface | USB 3.0 Gen 1, USB Type-C |
Supported operating systems | Windows 10/11 (64-bit), Linux Ubuntu 22.04 LTS |
Power supply | 12V DC, 6A (adapter included in the scope of delivery) |
Dimensions (W × H × D) | Approx. 20.5 × 5 × 25 cm (same housing as PCIe analyser) |
Weight (W × H × D) | Approx. 6 kg |
Status indicators | Link status LEDs per lane, trigger and activity indicator |
Documentation
Prodigy Exerciser & Analysis
