Offer

Description

Advanced Protocol Capture & Analysis for PCIe 5.0 Designs

The PCIe 5.0 Protocol Analyzer is engineered for design, validation, and debug of PCI Express-based systems operating at PCIe Gen5 data rates. Supporting analysis at speeds up to 32 GT/s, this analyzer enables engineers to capture, decode, and troubleshoot high-speed PCIe traffic with precision. By inserting high-performance interposers between the Root Complex and Endpoint (Device Under Test), you can record comprehensive protocol traces and accelerate time-to-market for your PCIe 5.0 products.

Features PCIe Gen5 Protocol Analyzer

Supports PCIe Gen1, Gen2, Gen3, Gen4, and PCIe 5.0 protocol decoding and analysis across x4 and x8 lane widths.
Enables analysis of four-lane and eight-lane PCI Express buses for Gen1 through Gen5 speeds.
Comes standard with M.2, U.2, CEM, E1.S, and SD Express interposers, validated for operation up to PCIe Gen5 (32 GT/s).
Provides comprehensive NVMe protocol decode functionality for PCIe-based storage applications.
Optional solder-down probe tips for four lanes, supporting PCIe speeds up to Gen3 (8 GT/s).
Decodes TS1, TS2, TLP, and DLLP packets, offering complete protocol-layer visibility.
Hardware-level protocol packet filtering for TS1, TS2, and IDLE sequences to optimize capture efficiency.
Software-based search, filter-in, and filter-out capabilities for faster traffic isolation and analysis.
Hardware protocol-aware trigger mechanisms based on TS1, TS2, TLP, and DLLP packet content.
Supports advanced multi-level if-then-else trigger logic for complex event detection.
Includes a standard 16 GB capture buffer, expandable up to 64 GB combined for TX and RX.
Offers detailed field-level views of every TLP and DLLP, enabling precise packet inspection.
Integrated LTSSM analysis for monitoring PCIe link training and state transitions.
Segmented memory architecture, allowing each capture segment to operate with a different trigger condition.
Provides a trigger-out signal to synchronize and trigger external instruments such as oscilloscopes.
Connects to the host system via USB 3.0 interface for high-speed data transfer.
Allows decoded protocol data to be exported in .txt format for further offline analysis.
Lightweight and portable design makes the protocol analyzer suitable for on-site and field testing.
Field-upgradeable platform supporting easy maintenance and remote firmware updates to access the latest features.

PCIe Protokoll Software

Productvideo

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Technical Data

Specification
Data Rates Supported	PCIe Gen1, Gen2, Gen 3, Gen 4. ( with Option PCIe4)
Link width	Four lanes (Four TX and Four RX).
Probes	Active M.2 Interposer (Standard) Solder Down Active Probes for speeds up to PCIe Gen3. (Optional)
Protocol Decode	TS1, TS2, TLP, DLLP,SDS, IDLE, EIOS, EIEOS, FTS, SKP
Trace Capture Size	Supports Continuous streaming of Protocol data to Host computer SSD/HDD. And Post Capture up to buffer size.
Trigger	Based on TS1, TS2, TLP, DLLP.
Connectors	Interface for Active probes. Trigger in/out SMA connectors.
Interface for Host Computer	USB3.0
Host Computer Requirements	Processor: Intel i7 10th Generation or better (Equivalent) Operating System: Windows 7/8.0/8.1/10 64bit OS. RAM: minimum 16GB but the product would give a faster response for 32GB/64GB/more. Storage: 256GB SSD or more (minimum storage capacity of 1GB should be available in the hard disk drive. User can use more storage based on trace storage requirement.) Display resolution: 1024X768. Interface: Host computer should support USB 3.0 interface.
Dimension	(W x H x D) (20.5X5X25) cm
Weight	Approx. 4 kg
Power Requirement	12V, 6A DC Power Supply (AC/DC Supplied along with Analyzer).