Protocol Decode Software offers extensive protocol decoding for MIPI-MPHY-UniPRO, LLI, and UFS protocol standards.
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Product number: PGY-UPRO
Manufacturer: Prodigy
Description
MIPI LLI Protocol Decode Software offers protocol decoding as specified in the MIPI LLI specification. PGY-MIPI LLI Protocol decode software runs in Tektronix Oscilloscope and provides measurements for protocol decode at the click of a button. This allows engineers to quickly check for MIPI LLI compliance and flexibility to debug the failure. In addition to this, engineers can decode the command and response of MIPI LLI to debug the communication. PGY-MIPI LLI takes advantage of the digital channels of MSO and provides the decoding of MIPI LLI data lines.
Features Unipro / UFS Protokollanalyzer
- UniPro and LLI Protocol Decoder enable faster system level protocol debugging
- Conforms to UniPro Protocol Specification version 1.6and LLI Protocol version 1.0
- Conforms to UFS Protocol Specification Version 2.0
- Supports NRZ (Non-Return-to-Zero) and PWM (Pulse Width Modulation) signalling schemes
- Configurable four-lane simultaneous protocol decode helps to correlate the lane to lane events
- Autolink of decoded data from list table to oscilloscope waveform for easy protocol debug at PHY layer
- Powerful UniPRO/LLI Protocol aware trigger features using Option ST6G serial trigger feature of oscilloscopes
- Triggering supports PWM, NRZ and 8b/10B encoded data schemes
- Detail view provides a comprehensive protocol and physical layer data correlation
- Frame listing and frame description provide comprehensive protocol layer information
- Each frame is displayed in detail as per UniPro and LLI Standard specification document
- Automated CRC computation to monitor CRC errors in the protocol packet
- Markers enable time measurement between messages in different lanes
- The software automatically identifies the signaling scheme and gear for hassle-free protocol analysis
- Bus diagram functions such as zoom, un-zoom, pan, fit to screen, and synchronize functions enable easy data analysis
- Supports oscilloscope live channels, Tektronix .wfm waveform files
- Generates comprehensive and customizable reports
- Ability to export the protocol details to txt and CSV file formats
Protocol View
The PGY-UPRO/LLI/UFS Protocol Decode Software offers extensive protocol decoding for MIPI-MPHY-UniPRO, LLI, and UFS protocol standards. This software offers Real-time hardware-based UniPRO/UFS Protocol aware triggers for PWM, NRZ, and 8B/10B data types. Now design and test engineers can automatically make accurate and reliable decode of multi-lane UniPRO/LLI/UFS using PGY-UPro/LLI/UFS software using data acquired by Tektronix, DPO/DSA/MSO70000 oscilloscope series to reduce the development and test cycle.
Seamless Integration with Tektronix Oscilloscope
PGY-UPRO/LLI/UFS runs inside the Tektronix oscilloscopes and decodes protocols and displays the decoded data of multiple lanes. This software links the decoded data to the electrical signal in the oscilloscope display. UniPRO/LLI Protocol-based trigger can be set up using the built-in high-speed serial trigger capabilities in Tektronix oscilloscopes.
UniPRO Protocol Aware Trigger
PGY-UPRO/LLI/UFS software provides protocol aware trigger conditions such as link start-up sequence, PHY adapter layer content and data link layer content. The unique capabilities in this software allow trigger data types such as PWM, NRZ or 8B/10B serial data of the protocol. PGY-UPRO supports the following Protocol Aware Trigger capabilities.
PGY-UFS Modul
PGY-UFS is module is an optional module to PGY-UPRO software, which provides protocol decode of UFS content present in the Data Link layer packet. PGY-UFS software extracts UFS information present in the data link packet and displays it in UFS Protocol Information Unit (UPIU). PGY-UFS has the flexibility of displaying only UFS protocol content or UFS and UniPRO data for easy debugging purposes.
Supported Tektronix oscilloscopes
- DPO 70000
- MSO 70000
- DSA 70000
| Trigger Event | Trigger Content |
|---|---|
| Link Start up Sequence (LSS) | Trigger on LSS Phase 1 (TRG_UPR_0) Trigger on LSS Phase 2 (TRG_UPR_1) Trigger on LSS Phase 3 (TRG_UPR_2) |
| PHY Adapter layer Content | PACP_PWR_req PACP_PWR_cnf PACP_cap_ind PACP_EPR_ind PACP_TEST_MODE_req PACP_GET_req PACP_GET_cnf PACP_SET_req PACP_SET_cnf PACP_Test_Data |
| Data Link layer Content | Data_SOF Data_COF AFC (Acknowledgement) NAC (No Acknowledgement) |
Documentation
Exerciser - Analyzer
100BASE-T1 Automotive Ethernet Protocol Analyzer
Product Nr.: PGY-100BASE-T1-PA
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Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Price on request
SPMI Protocol Analyzer and Exerciser
Product Nr.: PGY-SPMI-EX-PD
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Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser
- Supports SPMI v 1.0/ 2.0 specifications
- Ability to configure it as Master or Slave
- Supports Sole Master feature
- Supports Request Capable Slave (RCS) feature
- Supports the complex BUS arbitration process
- Generate different SPMI Packets
- Error injection such as parity error, ACK/NACK error, and Skip SSC error
- Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
- Simultaneously generate SPMI traffic and Protocol decode of the Bus
- Continuous streaming of protocol data to HDD/SSD
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol decoded data
- Ability to write exerciser script to combine multiple
- data frame generation at different data speeds
- USB2/3 host computer interface
- API support for automation in Python and C++
- Flexibility to upgrade to the unit for evolving SPMI Specification
- Optional Protocol Implementation Compliance Statement (PICS) supports scripts
Price on request
I2C/SPI Exerciser and Protocol Analyzer
Product Nr.: PGY-I2C/SPI-EX-PD
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Features I2C/SPI Protocol Analyzer and Exerciser
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Price on request
I3C Protocol Analyzer and Exerciser Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
I3C Protocol Analyzer and Exerciser (Light) Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD-Lite
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
JTAG Protocol Exerciser and Analyzer
Product Nr.: PGY-JTAG-EX-PD
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Features JTAG Protocol Analyzer and Exerciser
- Supports JTAG frequencies of up to 25MH
- Simultaneously generate JTAG traffic and Protocol decode of the Bus
- JTAG Master Capability
- Variable JTAG Data speeds and Duty cycle
- User-defined TCK & TDI Delays
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
PCIe Gen3/4 Protocol Analyzer
Product Nr.: PGY-PCIeGen3/4-PA
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Features PCIe Protocol Analyzer
- PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
- Currently supports four lane PCIeGen1/2/3/4 Bus.
- Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
- Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Trigger based on TS1, TS2, TLP and DLLP Packet content.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition¹.
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable enables the unit to easy maintain for latest feature set.
Price on request
PMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-PM-Bus-EX-PD
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Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Price on request
QSPI Exerciser and Protocol Analyzer
Product Nr.: PGY-QSPI-EX-PD
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Features QSPI Protocol Exerciser and Analyzer
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
RFFE Protocol Exerciser and Analyzer
Product Nr.: PGY-RFFE-EX-PD
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Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Price on request
SMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-SM-Bus-EX-PD
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Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer
- Supports SMBus 3.4Mbps Speed
- Ability to configure it as Master or Slave
- Simultaneously generate SMBus traffic and Protocol decode of the Bus
- SMBus Master and Slaves
- Error Injection ACK/NACK errors
- Variable SMBus data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
SMI (MDIO) Protocol Exerciser & Analysator
Product Nr.: PGY-SMI-EX-PD
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Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser
- Supports SMI (MDIO) speeds up to 25MHz
- Configuration as master or slave
- Simultaneous SMI traffic generation and protocol decoding
- Support for SMI clause 22 and 45
- Variable SMI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- Timing diagram of the protocol-decoded bus
- Listing view of log activity
- Ability to write a training script to combine the generation of multiple data frames at different data rates
- USB 2.0/3.0 interface for host computer
- API support for automation in Python or C++
Price on request
UART Protocol Exerciser and Analyzer
Product Nr.: PGY-UART-EX-PD
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Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request