SPI Software zur elektrischen Validierung und Protokolldekodierung mit Tektronix DPO5000, DPO7000, DPO/MSO/DSA 70000 und MSO5, MSO6 Oszilloskopen
€2,200.00*
Volume discounts on request!
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Further information
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Product number: PGY-SPI
Manufacturer: Prodigy
Description
Die Software zur elektrischen Validierung und Protokolldekodierung von SPI bietet elektrische Messungen zur Prüfung der Konformität und Protokolldekodierung gemäß der SPI-Spezifikation. Die PGY-SPI-Software zur elektrischen Validierung und Protokolldekodierung läuft auf den Tektronix Oszilloskopen DPO5000, TDS7000, DPO / DSA / MSO7000 und bietet elektrische Messungen und Protokolldekodierung mit nur einem Mausklick. Dies ermöglicht eine rasche Überprüfung der SPI-Konformität und Flexibilität bei der Fehlersuche. Darüber hinaus können sie den Command und die Response von SPI dekodieren, um die Kommunikation zu debuggen. PGY-SPI nutzt die Vorteile der digitalen Kanäle von MSO und ermöglicht die Dekodierung von SPI-Datenleitungen.
Features SPI Protokoll Software
- Automatisierte elektrische Messungen mit einem anpassbaren Referenzpegel des elektrischen SPI-Signals.
- Automatisierte Messungen unabhängig von der Geschwindigkeit des SPI-Busses
- Anpassbare Messgrenzwerteinstellung zur Pass/Fail-Validierung des elektrischen Signals, um Messungen bei unterschiedlichen Datengeschwindigkeiten zu ermöglichen.
- Dekodierung der SPI-Signale MOSI und MISO zum einfachen Verständnis des Protokolls
- Verknüpft den Protokollinhalt mit dem elektrischen Signal im Oszilloskop zum einfachen Erfassen der elektrischen Eigenschaften des Protokolls
- Überlagert die Protokolldaten auf der analogen Wellenform in einem Wellenform-Darstellungsfenster
- Vergrößert den Inhalt des ausgewählten SPI-Pakets in der Dekodierungstabelle im Waveform-Plot-Fenster zur einfachen Analyse der elektrischen Eigenschaften des SPI-Frames
- Anzeige von Protokoll- und Dekodierdaten in den Formaten Hexadezimal, Dezimal, Binär, Oktal und ASCII
- Möglichkeit, die SPI-Protokolldaten im CSV- und txt-Format zu speichern
- Utility-Funktionen wie Zoom, Rückgängig machen und Anpassen des Bildschirms für einfaches Debugging, während die Protokolldaten mit der Wellenform korreliert werden
- Erstellung von Berichten im HTML-Format
- Unterstützt WFM- und isf-Dateiformate für die Offline-Analyse
Detailansicht der SPI Dekodierung und Messung im Oszilloskop
Die PGY-SPI Software für elektrische Messungen und Protokolldekodierung bietet elektrische Messungen und Protokolldekodierung für SPI-Busse. Diese Software bietet die Flexibilität, Referenzpegel für elektrische Messungen und benutzerdefinierte Grenzwerte festzulegen, was sie zur vielseitigsten Lösung macht, um verschiedene Anforderungen an die Charakterisierung von SPI-Signalen zu erfüllen. Entwicklungs- und Testingenieure können jetzt automatisch genaue und zuverlässige elektrische Messungen durchführen und Protokolle in der PGY-SPI-Software dekodieren, indem sie Daten verwenden, die mit den Oszilloskopen der Serien DPO5000, TDS7000, DPO/DSA/MSO7000 von Tektronix erfasst wurden, um den Entwicklungs- und Testzyklus zu verkürzen.
Nahtlose Integration mit Tektronix-Oszilloskopen
Die PGY-SPI-Software läuft innerhalb der Tektronix-Oszilloskope und führt die elektrischen Messungen durch, dekodiert die Protokolle und zeigt die dekodierten Daten in einer Tabelle an und verknüpft die dekodierten Daten mit dem elektrischen Signal in der Wellenformdarstellung. Der auf dem SPI-Protokoll basierende Trigger kann mit den integrierten SPI-Trigger-Funktionen der Tektronix-Oszilloskope eingerichtet werden.
Referenz Level Setup
Für den SPI-Bus sind keine Standardmessgrenzen für Pass/Fail-Tests definiert. Die Grenzwerte variieren in Abhängigkeit von der SPI-Bus-Geschwindigkeit. Zur Charakterisierung und Validierung von SPI-Signalen bietet die PGYSPI-Software ein grafisches Messreferenzpegel-Setup zur Einstellung des Messreferenzpegels von SPI-Signalen. Diese Grenzwerte werden bei der Durchführung ausgewählter SPI-Messungen in der PGY-SPI-Software automatisch angewendet und verkürzen die Testzeit, indem sie zuverlässige Messungen ermöglichen.
Unterstützte Tektronix Oszilloskope
- DPO 5000
- DPO 7000
- MSO 7000
- DSA 7000
- MSO5
- MSO6
Technical Data
| Eigenschaften |  PGY-SPI Software |
|---|---|
| Elektrische Messungen |
|
| Busgeschwindigkeit | Benutzerdefiniert; begrenzt durch Oszilloskop-Bandbreite |
| Protokolldekodierung | Hexadezimal, Oktal, Binär, Dezimal, ASCII |
| Wellenformfenster | Überlagerung der Protokolldekodierungsdaten auf der Wellenform |
| Berichtserstellung | Anpassbarer Bericht im HTML-Format |
| Generierung von Berichten | Anpassbarer Bericht im HTML-Format |
| Export der Daten | CSV- und TXT-Format |
Documentation
Exerciser - Analyzer
100BASE-T1 Automotive Ethernet Protocol Analyzer
Product Nr.: PGY-100BASE-T1-PA
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Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Price on request
SPMI Protocol Analyzer and Exerciser
Product Nr.: PGY-SPMI-EX-PD
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Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser
- Supports SPMI v 1.0/ 2.0 specifications
- Ability to configure it as Master or Slave
- Supports Sole Master feature
- Supports Request Capable Slave (RCS) feature
- Supports the complex BUS arbitration process
- Generate different SPMI Packets
- Error injection such as parity error, ACK/NACK error, and Skip SSC error
- Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
- Simultaneously generate SPMI traffic and Protocol decode of the Bus
- Continuous streaming of protocol data to HDD/SSD
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol decoded data
- Ability to write exerciser script to combine multiple
- data frame generation at different data speeds
- USB2/3 host computer interface
- API support for automation in Python and C++
- Flexibility to upgrade to the unit for evolving SPMI Specification
- Optional Protocol Implementation Compliance Statement (PICS) supports scripts
Price on request
I2C/SPI Exerciser and Protocol Analyzer
Product Nr.: PGY-I2C/SPI-EX-PD
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Features I2C/SPI Protocol Analyzer and Exerciser
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Price on request
I3C Protocol Analyzer and Exerciser Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
I3C Protocol Analyzer and Exerciser (Light) Supports v1.0/v1.1 Specifications Ability to configure it as Master or Slave. Ability to configure BCR, LVR, and DCR registers. Simultaneously generate I3C traffic and Protocol decode of the Bus. Optional Compliance Test Specifications (CTS) test script support. Supports legacy I2C slaves and Master. Generate different I3C SDR and HDR Packets. Supports IBI and Hot Plug capabilities. Error Injection such as CRC errors, parity errors, and ACK/NACK errors. Variable I3C data speeds and duty cycle. PMIC device support as per JEDEC DDR5 spec requirement. Margin test capability: Voltage and timing variation. Continuous streaming of protocol data between the instrument and host computer. Timing diagram of Protocol decoded bus. Listing view of Protocol activity. Error Analysis in Protocol Decode. Ability to write exerciser script to combine multiple data frame generation at different data speeds. USB2/3 host computer interface. API support for automation in Python or C++.
Product Nr.: PGY-I3C-EX-PD-Lite
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Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
JTAG Protocol Exerciser and Analyzer
Product Nr.: PGY-JTAG-EX-PD
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Features JTAG Protocol Analyzer and Exerciser
- Supports JTAG frequencies of up to 25MH
- Simultaneously generate JTAG traffic and Protocol decode of the Bus
- JTAG Master Capability
- Variable JTAG Data speeds and Duty cycle
- User-defined TCK & TDI Delays
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
PCIe Gen3/4 Protocol Analyzer
Product Nr.: PGY-PCIeGen3/4-PA
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Features PCIe Protocol Analyzer
- PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
- Currently supports four lane PCIeGen1/2/3/4 Bus.
- Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
- Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Trigger based on TS1, TS2, TLP and DLLP Packet content.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition¹.
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable enables the unit to easy maintain for latest feature set.
Price on request
PMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-PM-Bus-EX-PD
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Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Price on request
QSPI Exerciser and Protocol Analyzer
Product Nr.: PGY-QSPI-EX-PD
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Features QSPI Protocol Exerciser and Analyzer
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
RFFE Protocol Exerciser and Analyzer
Product Nr.: PGY-RFFE-EX-PD
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Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Price on request
SMBus Protocol Exerciser and Analyzer
Product Nr.: PGY-SM-Bus-EX-PD
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Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer
- Supports SMBus 3.4Mbps Speed
- Ability to configure it as Master or Slave
- Simultaneously generate SMBus traffic and Protocol decode of the Bus
- SMBus Master and Slaves
- Error Injection ACK/NACK errors
- Variable SMBus data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
SMI (MDIO) Protocol Exerciser & Analysator
Product Nr.: PGY-SMI-EX-PD
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Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser
- Supports SMI (MDIO) speeds up to 25MHz
- Configuration as master or slave
- Simultaneous SMI traffic generation and protocol decoding
- Support for SMI clause 22 and 45
- Variable SMI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- Timing diagram of the protocol-decoded bus
- Listing view of log activity
- Ability to write a training script to combine the generation of multiple data frames at different data rates
- USB 2.0/3.0 interface for host computer
- API support for automation in Python or C++
Price on request
UART Protocol Exerciser and Analyzer
Product Nr.: PGY-UART-EX-PD
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Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request