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Description
With the industry's first oscilloscope-based PGY-HDMI-PA protocol analyzer software, you can see every event in the MHL/HDMI stream from the MHL/HDMI frame to the physical layer analog signals that traditional protocol analyzers cannot. PGY-HDMI-PA Protocol Analyzer software performs MHL/HDMI protocol conformance testing according to MHL CTS 1.1 and HDMI CTS 1.4a. It provides unmatched flexibility in analyzing, debugging, and correlating test results from MHL/HDMI frame to physical layer analog waveforms to address MHL/HDMI design challenges. For efficient troubleshooting, the PGY-HDMI-PA software provides a unique multi-viewer that includes a frame summary viewer, a frame viewer, a bus viewer, a protocol viewer, a data island viewer, and an event and test result viewer. The automatic linking between all these views allows you to see and correlate the data in different parts of the MHL/HDMI protocol stack. The PGY-HDMI-PA protocol analysis software, along with Tektronix physical layer conformance test solutions and the industry-leading Tektronix high-performance oscilloscope, provides a single-box solution for physical and protocol layer testing.
Features HDMI Protocol Software
- MHL/HDMI Protocol analysis software offers in-depth visibility from the physical layer to video frames with unmatched data correlation between all the layers of MHL/HDMI protocol.
- Transforms the general-purpose oscilloscope into a sophisticated MHL/HDMI Protocol Analyzer.
- Debugging and troubleshooting are made easy by cross-correlating the MHL/HDMI protocol data using a frame summary viewer, frame viewer, Bus viewer, data packet, and event viewer.
- Frame summary view helps to locate error frames for detailed analysis quickly.
- The Frame Viewer helps to view the transmitted frame with color-coded MHL/HDMI operating modes as per the specification and eliminates the need for a Sink device in MHL/HDMI test setup by reproducing the transmitted image in an Oscilloscope display.
- Bus viewer with the Physical layer analog waveforms offers unmatched flexibility in correlating protocol errors with the physical layer.
- The Protocol Viewer displays the tabular view of protocol information with decoded values.
- The Event Viewer lists detailed protocol errors and events in the MHL/HDMI compliance tests to quickly locate the protocol failures.
- Raw and detailed packet information in the Data packet viewer helps to identify the problems in Data Island periods.
- Supports 24, 30, 36, and 48 bits per video pixel for HDMI and 24 bits per pixel for MHL.
- The oscilloscope setup assistant automatically sets up the oscilloscope to obtain accurate and reliable test results.
- Performs the protocol Tests per the MHL Compliance Test specification 1.1 and HDMI Compliance Test specification 1.4a and displays quick Pass/Fail results.
- Conforms to HDMI Specification 1.4a and MHL Specification 1.1.
- Supports Oscilloscope live channels, Tektronix .wfm waveform files, and .bin (P/A/V file format of HDMI Capture card) files Generates comprehensive and customizable reports.
- Ability to export the analyzed data to .bmp, txt, CSV, .bin (P/A/V File format) for advanced analysis.
In-depth MHL/HDMI protocol analysis
For efficient MHL/HDMI protocol debugging and optimization, the PGY-HDMI-PA protocol analysis software has a frame summary viewer, frame viewer, bus viewer, protocol viewer, data packet viewer, and event and test result viewers.
The Frame Summary Viewer shows a thumbnail image for each frame with a summary of the pass/fail test results of the corresponding frame. The view allows you to quickly navigate to the failed frames for detailed analysis.
The Frame Viewer displays the transmitted full image according to the MHL/HDMI specification. For easy identification of the operation modes, the control period, preamble video, preamble data, data protection band, data island and video protection band, and active video are displayed in different colors. Hovering the mouse over the image gives the type of each mode, relative pixel information, the transmitted 10-bit data value, and the corresponding decoded information for that mode. The image viewer eliminates the need for an MHL/HDMI sync device to display the image transmitted from the source.
Frame View
The Frame Viewer displays the transmitted full image according to the MHL/HDMI specification. For easy identification of the operation modes, the control period, preamble video, preamble data, data protection band, data island and video protection band, and active video are displayed in different colors. Hovering the mouse over the image gives the type of each mode, relative pixel information, the transmitted 10-bit data value, and the corresponding decoded information for that mode. The image viewer eliminates the need for an MHL/HDMI sync device to display the image transmitted from the source.
Bus Viewer
The Bus Viewer provides a way to visually review the transmitted MHL/HDMI information in the bus diagram display along with the analog waveforms. The industry's first MHL/HDMI bus diagram and analog waveform with overlapping log data help identify issues related to data skew between pairs and skew between clock and data. Each line is color coded for control period, preamble video, preamble data, data guard band, data island and video guard band, active video for easy error detection. In addition to the bus information, the HDMI bus viewer also provides information about the active periods of H-Sync and V-Sync. The MHL Bus Viewer allows you to view the Data Positive and Data Negative waveforms, as well as the corresponding common mode and data created using the captured MHL signals. The MHL bus diagram also shows the details of the transmitted multiplexed logical channel as well as the demultiplexed logical channels according to the MHL protocol specification. To identify and locate errors in a specific period, the bus viewer provides the pixel index in the selected frame, the line number and the pixel index in the line. Utility functions such as Zoom, Un-Zoom, Pan, Undo, Fit horizontal, Fit vertical, Fit horizontal and vertical and Side-by-Side Waveform and Bus View help to maneuver the bus graph and analyze the MHL/HDMI protocol.
Protocol Viewer
The protocol viewer provides a tabular view of the protocol list with transmitted 10-bit data for each channel along with the decoded 8-bit data for active video, 4-bit TERC4 data for the data island, and 2-bit data for the control period encoding along with the time stamp.
Data Packet Viewer
The data packet viewer lists the entire data packets that were transmitted in the selected frame. Each data island period type, the line number, the pixel number and the BCH data of the data island period are displayed in tabular form. Depending on the packet type, the data packet viewer also provides the details of the data packet according to the CEA 861 specification. The software also performs comprehensive tests according to HDMI conformance test specification 1.4a and MHL conformance test specification 1.1.
Event and Test results viewer
The event and test result display lists the selected test results together with the description of the individual information on passed and failed tests.
Seamless oscilloscope integration
HDMI Protocol Analysis Software runs inside the Tektronix high-performance Windows Oscilloscope. The Oscilloscope Setup Wizard helps automatically set up the oscilloscope for reliable and accurate test results. It provides the flexibility to capture 2-second video frames according to the MHL/HDMI test procedure or a few frames for quick troubleshooting.
Automatically customizable report and export
The MHL/HDMI software's built-in automatic report generator provides a customizable report creation feature that helps effectively distribute the test report among other team members and management.
Protocol check
The MHL/HDMI software's built-in automatic report generator provides a customizable report generation function that helps communicate test reports effectively between other team members and management. For further data analysis, the software also provides image, log, and data island period data in multiple export formats. The P/A/V binary format helps cross-correlate the PGY-HDMI-PA data using conventional protocol analysis software.
Supported Tektronix Oscilloscopes
- DPO 70000
- MSO 70000
- DSA 70000
Documentation
Exerciser - Analyzer
Features 100BASE-T1 Protocol Analyzer
- Protocol decode and Analysis of 100BASE-T1 Bus.
- Passive tapping allows a non-intrusive method of monitoring the 100BASE-T1 Bus.
- Powerful multi-layer protocol layer trigger capabilities enable capturing data at specific events.
- Decoding of TC10 Sleep and Wakeup events of master and slave.
- Continuous streaming of protocol activity SSD/HDD enables long-duration capture of protocol data.
- Simultaneously monitoring of 100BASE-T1 and MDIO/MDC protocol activity.
- Live protocol decode capabilities allow you to view the protocol information while the test case actively running in DUT.
- The analytics feature provides statistical information on protocol packets.
- FCS error report helps in monitoring the protocol errors.
- The simplified Protocol Listing view with search and filter capabilities is easy to use.
- Software and firmware are fields upgradable
- Report generation.
Price on request
Features PGY-SPMI-EX-PD SPMI Protocol Analyzer and Exerciser
- Supports SPMI v 1.0/ 2.0 specifications
- Ability to configure it as Master or Slave
- Supports Sole Master feature
- Supports Request Capable Slave (RCS) feature
- Supports the complex BUS arbitration process
- Generate different SPMI Packets
- Error injection such as parity error, ACK/NACK error, and Skip SSC error
- Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
- Simultaneously generate SPMI traffic and Protocol decode of the Bus
- Continuous streaming of protocol data to HDD/SSD
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol decoded data
- Ability to write exerciser script to combine multiple
- data frame generation at different data speeds
- USB2/3 host computer interface
- API support for automation in Python and C++
- Flexibility to upgrade to the unit for evolving SPMI Specification
- Optional Protocol Implementation Compliance Statement (PICS) supports scripts
Price on request
Features I2C/SPI Protocol Analyzer and Exerciser
- Supports I2C Specifications
- Supports SPI Specifications
- Ability to configure it as Master/Slave
- Generate different I2C/SPI Packets
- Variable data speeds
- Generate I2C/SPI traffic and protocol decode of the bus
- A timing diagram of the protocol decoded bus
- Listing view of protocol activity
- Ability to write exerciser script to combine multiple frame generation at different data speeds
- USB 2/3 host computer interface
- Continuous streaming of protocol activity to host system HDD/SSD
- API support for automation in python or C#
Price on request
Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
Features I3C Protocol Analyzer und Exerciser
*v1.1 supports only one lane commands
Price on request
Features JTAG Protocol Analyzer and Exerciser
- Supports JTAG frequencies of up to 25MH
- Simultaneously generate JTAG traffic and Protocol decode of the Bus
- JTAG Master Capability
- Variable JTAG Data speeds and Duty cycle
- User-defined TCK & TDI Delays
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
Features PCIe Protocol Analyzer
- PCIe Gen1/2/3/4-X4 Protocol Decode and Analysis.
- Currently supports four lane PCIeGen1/2/3/4 Bus.
- Active M.2 Connector interposer for speeds up to PCIe Gen4 is standard offering with protocol analyzer.
- Optional Passive M.2 Connector interposer for speeds up to PCIe Gen3.
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet TS1, TS2 and IDLE filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Trigger based on TS1, TS2, TLP and DLLP Packet content.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition¹.
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable enables the unit to easy maintain for latest feature set.
Price on request
Features PGY-PMBus-EX-PD PM Protokoll Exerciser and Analyzer
- Supports PMBus Specifications.
- Ability to configure it as Master/Slave.
- Variable data speeds.
- Generate PMbus traffic and protocol decode of the bus.
- A timing diagram of the protocol decoded bus.
- Listing view of protocol activity.
- Ability to write exerciser script to combine multiple frame generation at different data speeds.
- USB 2/3 host computer interface.
- Continuous streaming of protocol data to host computer to provide a large buffer.
- API support for automation in python or C++.
Price on request
Features QSPI Protocol Exerciser and Analyzer
- Supports QSPI speeds of up to 80MHz*
- Ability to configure it as Master or Slave
- Simultaneously generate QSPI traffic and Protocol decode of the Bus
- QSPI Master and Slaves
- STR and DTR Transfer rates
- Extended, Dual, and Quad QSPI Modes Supported
- Variable QSPI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer in sniffer mode
- The timing diagram of the protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
Features RFFE Protocol Analyzer and Exerciser
- Supports RFFE2.0/2.1 Specification
- Ability to configure it as Master or Slave
- Generate different RFFE at full speed and half of full frequency speed
- Error Injection such as parity errors and ACK/NACK errors
- Variable RFFE data speeds
- Simultaneously generate RFFE traffic and Protocol decode of the Bus
- The timing diagram of the Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB2/3 host computer interface
- Flexibility to upgrade to the unit for evolving RFFE Specification
Price on request
Features PGY-SMBus-EX-PD SM Protokoll Exerciser and Analyzer
- Supports SMBus 3.4Mbps Speed
- Ability to configure it as Master or Slave
- Simultaneously generate SMBus traffic and Protocol decode of the Bus
- SMBus Master and Slaves
- Error Injection ACK/NACK errors
- Variable SMBus data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request
Features PGY-SMI-EX-PD SMI Protocol Analyzer and Exerciser
- Supports SMI (MDIO) speeds up to 25MHz
- Configuration as master or slave
- Simultaneous SMI traffic generation and protocol decoding
- Support for SMI clause 22 and 45
- Variable SMI data speeds and duty cycle
- Continuous streaming of protocol data to the host computer to provide a large buffer
- Timing diagram of the protocol-decoded bus
- Listing view of log activity
- Ability to write a training script to combine the generation of multiple data frames at different data rates
- USB 2.0/3.0 interface for host computer
- API support for automation in Python or C++
Price on request
Features PGY-UART-EX-PD UART Protokoll Exerciser and Analyzer
- Supports custom UART traffic generation
- Simultaneously generate UART traffic and Protocol decode of the bus
- Variable UART baud rates
- Continuous streaming of protocol data to the host computer to provide a large buffer
- A timing diagram of Protocol decoded bus
- Listing view of Protocol activity
- Error Analysis in Protocol Decode
- Ability to write exerciser script to combine multiple data frame generation at different data speeds
- USB 2.0/3.0 host computer interface
- API support for automation in Python or C++
Price on request